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| HANBit HMN1M8DV Non-Volatile SRAM MODULE 8Mbit (1024k x 8bit) 36Pin - DIP, 3.3V Part No. HMN1M8DV GENERAL DESCRIPTION The HMN1M8DV Nonvolatile SRAM is a 8,388,608-bit static RAM organized as 1,048,576 bytes by 8 bits. The HMN1M8DV has a self-contained lithium energy source provide reliable non-volatility coupled with the unlimited write cycles of standard SRAM and integral control circuitry which constantly monitors the single 3.3V supply for an out-oftolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the memory until after VCC returns valid and write protection is unconditionally enabled to prevent garbled data. In addition the SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source is switched on to sustain the memory until after VCC returns valid. The HMN1M8DV uses extremely low standby current CMOS SRAM's, coupled with small lithium coin cells to provide nonvolatility without long write-cycle times and the write-cycle limitations associated with EEPROM. FEATURES w Access time : 70, 85, 120, 150 ns w High-density design : 8Mbit Design w Battery internally isolated until power is applied w Industry-standard 36-pin 1,024K x 8 pinout w Unlimited write cycles w Data retention in the absence of VCC w 10-years minimum data retention in absence of power w Automatic write-protection during power-up/power-down cycles w Data is automatically protected during power loss PIN ASSIGNMENT NC NC A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VCC A19 NC A15 A17 /WE A13 A8 A9 A11 /OE A10 /CE DQ7 DQ6 DQ5 DQ4 DQ3 OPTIONS w Timing 70 ns 85 ns 120 ns 150 ns MARKING - 70 - 85 -100 -150 36-pin Encapsulated Package URL:www.hbe.co.kr Rev.0.0 (FEBRUARY/ 2002) 1 HANBit Electronics Co.,Ltd HANBit FUNCTIONAL DESCRIPTION HMN1M8DV The HMN1M8DV executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by the address inputs(A0-A19) defines which of the 1,048,576 bytes of data is accessed. Valid data will be available to the eight data output drivers within tACC (access time) after the last address input signal is stable. When power is valid, the HMN1M8DV operates as a standard CMOS SRAM. During power-down and power-up cycles, the HMN1M8DV acts as a nonvolatile memory, automatically protecting and preserving the memory contents. The HMN1M8DV is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs are stable. The later occurring falling edge of /CE or /WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle. /WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The /OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled (/CE and /OE active) then /WE will disable the outputs in tODW from its falling edge. The HMN1M8DV provides full functional capability for Vcc greater than 3.0 V and write protects by 2.8 V nominal. Powerdown/power-up control circuitry constantly monitors the Vcc supply for a power-fail-detect threshold VPFD. When VCC falls below the VPFD threshold, the SRAM automatically write-protects the data. All inputs to the RAM become "don't care" and all outputs are high impedance. As Vcc falls below approximately 2.5V, the power switching circuit connects the lithium energy soure to RAM to retain data. During power-up, when Vcc rises above approximately 2.5 volts, the power switching circuit connects external Vcc to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after Vcc exceeds 3.0 volts. BLOCK DIAGRAM PIN DESCRIPTION /OE /WE 2 x 512K x 8 SRAM Block Power A0-A19 DQ0-DQ7 A0-A19 : Address Input /CE : Chip Enable VSS : Ground DQ0-DQ7 : Data In / Data Out /CE CON VCC /WE : Write Enable /OE : Output Enable VCC: Power (+5V) NC : No Connection /CE A19 Power - Fail Control Lithium Cell URL:www.hbe.co.kr Rev.0.0 (FEBRUARY/ 2002) 2 HANBit Electronics Co.,Ltd HANBit TRUTH TABLE MODE Not selected Output disable Read Write /OE X H L X /CE H L L L /WE X H H L HMN1M8DV I/O OPERATION High Z High Z DOUT DIN POWER Standby Active Active Active ABSOLUTE MAXIMUM RATINGS PARAMETER DC voltage applied on VCC relative to VSS DC Voltage applied on any pin excluding VCC relative to VSS Operating temperature Storage temperature Soldering temperature SYMBOL VCC VT TOPR TSTG TSOLDER RATING -0.5V to Vcc+0.5 -0.3V to 4.6V 0 to 70C -65C to 150C 260C For 10 second VT VCC+0.3 CONDITIONS NOTE: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. RECOMMENDED DC OPERATING CONDITIONS ( TA= TOPR ) PARAMETER Supply Voltage Ground Input high voltage Input low voltage SYMBOL VCC VSS VIH VIL MIN 3.0V 0 2.2 -0.3 TYPICAL 3.3V 0 MAX 3.6V 0 VCC+0.3 0.6V NOTE: Typical values indicate operation at TA = 25 CAPACITANCE (TA=25 , f=1MHz, VCC=3.3V) DESCRIPTION Input Capacitance Input/Output Capacitance 1. Only sampled, not 100% tested CONDITIONS Input voltage = 0V Output voltage = 0V SYMBOL CIN CI/O MAX 8 10 MIN UNIT pF pF URL:www.hbe.co.kr Rev.0.0 (FEBRUARY/ 2002) 3 HANBit Electronics Co.,Ltd HANBit HMN1M8DV DC ELECTRICAL CHARACTERISTICS (TA= TOPR, VCCmin VCC VCCmax ) PARAMETER Input Leakage Current Output Leakage Current Output high voltage Output low voltage Power-fail Deselect Voltage CONDITIONS VIN=VSS to VCC /CE=VIH or /OE=VIH or /WE=VIL IOH=-1.0mA IOL= 2.0mA Threshold Voltage (THS = VSS ) Standby supply current /CE=2.2v /CE VCC-0.2V, Standby supply current Operating current Supply switch-over voltage Power supply 0V VIN 0.2V, or VIN VCC-0.2V /CE=VIL, II/O=0 , VIN = VIL or VIH, Read ICC VSO 2.5 12 V ISB1 30 mA ISB 0.6 Select VPFD 2.8 2.9 3.0 V SYMBOL ILI ILO VOH VOL MIN 2.4 TYP. MAX 3.0 3.0 0.4 UNIT mA mA V V CHARACTERISTICS (Test Conditions) +5V +5V DOUT 100 1.9K 5 PARAMETER Input pulse levels Input rise and fall times Input and output timing reference levels Output load (CL =30pF+1TTL) (CL =100pF+1TTL) 1) 1) VALUE 0.4 to 2.2V 5 ns 5V ( unless otherwise specified) See Figures DOUT 1.9K 1K 1K Figure 1. Output Load A Figure 2. Output Load B Note : Including scope and jig capacitance URL:www.hbe.co.kr Rev.0.0 (FEBRUARY/ 2002) 4 HANBit Electronics Co.,Ltd HANBit READ CYCLE (TA= TOPR, VCCmin VCC VCCmax ) PARAMETER Read Cycle Time Address Access Time Chip enable access time Output enable to Output valid Chip enable to output in low Z Output enable to output in low Z Chip disable to output in high Z Output disable to output high Z Output hold from address change SYMBOL tRC tACC tACE tOE tCLZ tOLZ tCHZ tOHZ tOH Output load A Output load A Output load A Output load B Output load B Output load B Output load B Output load A CONDITIONS -70 MIN 70 5 5 0 0 10 MAX 70 70 35 25 25 MIN 85 5 0 0 0 10 -85 MAX 85 85 45 35 25 - HMN1M8DV -120 MIN 120 5 0 0 0 10 MAX 120 120 60 45 35 - -150 MIN 150 10 5 0 0 10 MAX 150 150 70 60 50 - UNIT ns ns ns ns ns ns ns ns ns WRITE CYCLE (TA= TOPR, Vccmin Vcc Vccmax ) PARAMETER Write Cycle Time Chip enable to end of write Address setup time Address valid to end of write Write pulse width Write recovery time (write cycle 1) Write recovery time (write cycle 2) Data valid to end of write Data hold time (write cycle 1) Data hold time (write cycle 2) Write enabled to output in high Z Output active from end of write SYMBOL tWC tCW tAS tAW tWP tWR1 tWR2 tDW tDH1 tDH2 tWZ tOW Note 4 Note 4 Note 5 Note 5 Note 1 Note 2 Note 1 Note 1 Note 3 Note 3 CONDITIONS -70 MIN 70 65 0 65 55 5 15 30 0 10 0 5 MAX 25 MIN 85 75 0 75 65 5 15 35 0 10 0 0 -85 MAX 30 -120 MIN 120 100 0 100 85 5 15 45 0 10 0 0 MAX 40 -150 Min 150 100 0 90 90 5 15 50 0 0 0 5 Max 50 UNI T ns ns ns ns ns ns ns ns ns ns ns ns NOTE: 1. A write ends at the earlier transition of /CE going high and /WE going high. 2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at the later transition of /CE going low and /WE going low. 3. Either tWR1 or tWR2 must be met. 4. Either tDH1 or tDH2 must be met. 5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain in highimpedance state. URL:www.hbe.co.kr Rev.0.0 (FEBRUARY/ 2002) 5 HANBit Electronics Co.,Ltd HANBit POWER-DOWN/POWER-UP CYCLE PARAMETER VPFD(max) to VPFD(min) VCC Fail Time VPFD(max) to VSS VCC Fail Time VPFD(max) to VPFD(min) VCC Rise Time Write Protect Time SYMBOL tF tFB tR Delay after Vcc slews down tWPT past VPFD before SRAM is Write-protected. Chip Enable Recovery VSS to VPFD (min) VCC Rise Time tCER tRB 40 1 40 CONDITIONS MIN 300 150 10 HMN1M8DV TYP. - MAX - UNIT ms ms ms ms 250 - 120 - ms ms TIMING WAVEFORM - READ CYCLE NO.1 (Address Access)*1,2 tRC Address tACC tOH DOUT Previous Data Valid Data Valid - READ CYCLE NO.2 (/CE Access)*1,3,4 /CE tACE tCLZ DOUT High-Z tRC tCHZ High-Z URL:www.hbe.co.kr Rev.0.0 (FEBRUARY/ 2002) 6 HANBit Electronics Co.,Ltd HANBit - READ CYCLE NO.3 (/OE Access)*1,5 tRC Address tACC /OE tOE DOUT tOLZ High-Z tOHZ Data Valid HMN1M8DV High-Z NOTES: 1. /WE is held high for a read cycle. 2. Device is continuously selected: /CE = /OE =VIL. 3. Address is valid prior to or coincident with /CE transition low. 4. /OE = VIL. 5. Device is continuously selected: /CE = VIL - WRITE CYCLE NO.1 (/WE-Controlled)*1,2,3 tWC Address tAW tCW /CE tAS /WE tDW DIN tWZ DOUT Data Undefined (1) Data-in Valid tOW High-Z tDH1 tWP tWR1 URL:www.hbe.co.kr Rev.0.0 (FEBRUARY/ 2002) 7 HANBit Electronics Co.,Ltd HANBit - WRITE CYCLE NO.2 (/CE-Controlled)*1,2,3,4,5 HMN1M8DV Address tAS /CE tWP /WE tDW DIN tWZ DOUT Data NOTE: tAW tCW tWR2 tDH2 Data-in Undefined High-Z 1. /CE or /WE must be high during address transition. 2. Because I/O may be active (/OE low) during this period, data input signals of opposite polarity to the outputs must not be applied. 3. If /OE is high, the I/O pins remain in a state of high impedance. 4. Either tWR1 or tWR2 must be met. 5. Either tDH1 or tDH2 must be met. POWER-DOWN/POWER-UP TIMING VCC 4.75 VPFD tPF VPFD 4.25 VSO tFS tWPT tDR VSO tPU tCER /CE URL:www.hbe.co.kr Rev.0.0 (FEBRUARY/ 2002) 8 HANBit Electronics Co.,Ltd HANBit HMN1M8DV PACKAGE DIMENSION Dimension A B C D E F G H I J Min 2.070 0.710 0.365 0.015 0.008 0.590 0.017 0.090 0.080 0.120 Max 2.100 0.740 0.375 0.013 0.630 0.023 0.110 0.110 0.150 J A I H G C D B E F All dimensions are in inches. ODERING INFORMATION H M N 1 M 8 DV - 70 I Operating Temperature : I = Industrial Temp. (-40~85 C ) Blank = Commercial Temp. (0~70C) Speed options : 70 = 70 ns 85 = 85ns 120 = 120ns 150 = 150ns 3.3V Dip type package Device : 1,024K x 8 bit Nonvolatile SRAM HANBit Memory Module URL:www.hbe.co.kr Rev.0.0 (FEBRUARY/ 2002) 9 HANBit Electronics Co.,Ltd |
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